This invention relates to a shift circuit for use in a packed nine-bit-byte data processing system. The nine-bit-byte data are usually representative of binary-coded decimal numbers, respectively.
A packed nine-bit-byte decimal data processing system is disclosed in U.S. Pat. No. 4,251,864 issued to Jerry L. Kindell et al and assigned to Honeywell Information Systems Inc. The system comprises means for carrying out transformation between two data formats.
As will later be described with reference to one of several figures of the accompanying drawing, a datum of one of the data formats is given by a bit sequence of a prescribed number of nine-bit bytes, such as eight nine-bit bytes, consecutively arranged from the most significant bit of the sequence to the least significant bit thereof. Each nine-bit byte consists of a prescribed binary bit, a first four-bit byte, and a second four-bit byte which are consecutively arranged in a direction or sense from the most significant bit to the least significant bit. The prescribed binary bit is representative of a prescribed one of two binary numbers, such as binary zero and one.
Before subjecting such a datum to an arithmetic operation, the datum is transformed into a datum of the other data format. The transformed datum is given by another bit sequence of eight-bit bytes. More particularly, each nine-bit byte is transformed into an eight-bit byte by stripping the prescribed binary bit from the nine-bit byte under consideration.
Such transformed data are supplied to a decimal arithmetic unit and furthermore to a shift circuit and are subjected to an arithmetic operation specified by an instruction. Upon completion of the arithmetic operation, a resulting datum is given by a resulting bit sequence of eight-bit bytes and is inverse-transformed into a bit sequence of nine-bit bytes.
Two cyceles are therefore indispensable in the Kindell et al system for the transformation and the inverse transformation before and after each arithmetic operation. An accordingly long time is necessary on completing execution of each instruction. In other words, the data processing system has not a high data processing speed. In addition, the hardware architecture is inevitably rendered intricate by the means for carrying out transformation between the two data formats.